Exemplary embodiments relate generally to pipelined data transfer operations, and particularly to systems and methods for monitoring performance in a shared pipeline.
In computing, a pipeline may be considered as a set of data processing elements connected in series, so that the output of one element is the input of the next one. The elements of a pipeline are often executed in parallel or in time-sliced fashion; in that case, some amount of buffer storage is often inserted between elements.
Further, an instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput (the number of instructions that can be executed in a unit of time). Pipelining involves splitting the processing of a computer instruction into a series of independent steps, with storage at the end of each step. This allows the computer's control circuitry to issue instructions at the processing rate of the slowest step, which is much faster than the time needed to perform all steps at once.
In a system utilizing a shared pipeline, commands are processed by a variety of controllers which take turns accessing the shared pipeline. Each controller contains many registers containing information about the type and state of the command. Each controller may also contain error checking and recovery logic for every field it presents to the shared pipeline. When a parity error was detected on a field within a controller, the controller could take appropriate recovery action. However, parity errors detected in the shared pipeline are generally not recoverable, and thus such parity errors could result in the most extreme and undesirable recovery action—system checkstop.